The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Mar. 02, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyeonghoon Park, Suwon-si, KR;

Inhwan Baek, Suwon-si, KR;

Jaebok Baek, Suwon-si, KR;

Jeehoon Han, Suwon-si, KR;

Seungyoon Kim, Suwon-si, KR;

Heesuk Kim, Suwon-si, KR;

Byoungjae Park, Suwon-si, KR;

Jongseon Ahn, Suwon-si, KR;

Jumi Yun, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.


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