The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Dec. 28, 2022
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Liang Chen, Wuhan, CN;
Wei Liu, Wuhan, CN;
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Abstract
A three-dimensional (3D) memory device includes an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and the memory array layer having a plurality of memory cells and a stair structure. The memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one driver region. The 3D memory device further includes CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices. The CMOS wafer includes at least one page buffer region. The array wafer and the CMOS wafer are bonded at a bonding interface.