Volatile memory, system on chip and electronic device comprising the same

Abstract

A volatile memory device comprises a memory cell array including a plurality of memory cells storing data, and control logic controlling read and write operations for the plurality of memory cells. The control logic is configured to receive a command instructing a self-refresh operation from an external host device, to perform the self-refresh operation in response to the received command, to request the external host device to transfer data stored in the plurality of memory cells in response to a performance time of the self-refresh operation having elapsed a first threshold time, to monitor a read command received from the external host device in response to receiving a notification of self-refresh operation termination and a read command from the external host device, and to enter a power off state in response to the read command not being received for a second threshold time.