The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Sep. 14, 2021
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Hirohiko Watanabe, Hachioji, JP;

Shunsuke Saito, Hachioji, JP;

Yoshitaka Nishimura, Azumino, JP;

Fumihiko Momose, Higashi-chikuma-gun, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 76/15 (2026.01); B23K 35/02 (2006.01); B23K 35/26 (2006.01); C22C 13/02 (2006.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 72/50 (2026.01); H10W 74/00 (2026.01); H10W 95/00 (2026.01);
U.S. Cl.
CPC ...
C22C 13/02 (2013.01); B23K 35/0244 (2013.01); B23K 35/025 (2013.01); B23K 35/26 (2013.01); B23K 35/262 (2013.01); H10W 76/15 (2026.01); H10W 72/325 (2026.01); H10W 72/352 (2026.01); H10W 72/5363 (2026.01); H10W 72/884 (2026.01); H10W 74/00 (2026.01); H10W 95/00 (2026.01);
Abstract

A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, an element selected from the group consisting of: more than 0 and 1.0% by mass or less of Si, more than 0 and 0.1% by mass or less of V, 0.001 to 0.1% by mass of Ge, 0.001 to 0.1% by mass of P, and more than 0 and 1.2% by mass or less of Cu, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.


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