The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Apr. 07, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Choongbin Yim, Seoul, KR;

Jongbo Shim, Asan-si, KR;

Jihwang Kim, Cheonan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 23/3107 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/5389 (2013.01); H01L 23/562 (2013.01);
Abstract

A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including a core layer, an upper wiring layer, a plurality of dummy structures, and a solder resist layer, wherein the core layer has through-holes, wherein the plurality of dummy structures are disposed in the through-holes and are electrically insulated from the upper wiring layer, and wherein the solder resist layer covers the upper wiring layer and extends in the through-holes; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant disposed between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure; and a connection bump disposed on the lower substrate.


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