The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Nov. 15, 2022
Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

Manish Nayini, Wappingers Falls, NY (US);

Janak G. Patel, South Burlington, VT (US);

Richard S Graf, Gray, ME (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/13 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/485 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 21/4853 (2013.01); H01L 23/145 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/562 (2013.01);
Abstract

An integrated circuit (IC) package comprises: at least two substrate sub-units configured to adjoin each other to form a substrate, each substrate sub-unit comprising electrical traces configured to couple i) to corresponding terminals of an integrated circuit component and ii) to corresponding terminals of an interposer or a printed circuit board; at least one coupler configured to: 1) align the substrate sub-units and 2) join the substrate sub-units together to form the substrate from the at least two substrate sub-units; and, an integrated circuit having terminals and configured to electrically couple to terminals of the substrate formed of at least two substrate sub-units.


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