The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Dec. 16, 2021
Applicant:

Hitachi Energy Ltd, Zürich, CH;

Inventors:

Slavo Kicin, Zürich, CH;

Gernot Riedel, Baden-Rütihof, CH;

Jürgen Schuderer, Zürich, CH;

Fabian Mohn, Ennetbaden, CH;

Assignee:

HITACHI ENERGY LTD, Zürich, CH;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 22/22 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/5382 (2013.01); H01L 25/072 (2013.01);
Abstract

A power semiconductor module (), comprising a substrate () which carries a plurality of power semiconductor devices (), wherein the plurality of power semiconductor devices () comprises a first group of power semiconductor devices () and a second group of at least one power semiconductor device (). The first group of power semiconductor devices () consists of at least two non-damaged power semiconductor devices (), and the second group of power semiconductor devices () consists of at least one damaged power semiconductor device (). The at least two non-damaged power semiconductor devices () are electrically interconnected in a parallel configuration, and the second group of at least one power semiconductor device () is electrically separated from the members of the first group of power semiconductor devices (). The disclosure further relates to an electrical converter and a method for manufacturing a power semiconductor module ().


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