The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2026
Filed:
May. 28, 2021
Plessey Semiconductors Ltd, Plymouth, GB;
Andrea Pinos, Plymouth, GB;
Samir Mezouari, Plymouth, GB;
Weisin Tan, Plymouth, GB;
John Lyle Whiteman, Plymouth, GB;
Plessey Semiconductors Ltd, Plymouth Devon, GB;
Abstract
A monolithic LED array precursor comprising a plurality of LED structures sharing a first semiconductor layer, wherein the first semiconductor layer defines a plane of the LED array precursor, each LED structure comprising (i) a second semiconductor layer on the first semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the second semiconductor layer has sloped sides, (ii) a third semiconductor layer on the second semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the third semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the third semiconductor layer has sloped sides parallel to the sloped sides of the second semiconductor layer, (iii) a fourth semiconductor layer on the third semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the fourth semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the fourth semiconductor layer has sloped sides parallel to the sloped sides of the third semiconductor layer, (iv) a primary electrical contact on the fourth semiconductor layer, wherein the contact is only on the upper surface portion of the fourth semiconductor layer which is parallel to the plane of the LED array precursor, (v) electrically insulating, optically transparent spacers on the sloped sides of the fourth semiconductor layer, the spacers having an internal surface facing the sloped sides of the fourth semiconductor layer and an opposing external surface and (vi) a reflecting layer, electrically conducting extending over the external surface of the spacers, wherein the third semiconductor layer comprises a plurality of quantum well sub-layers, the quantum well sub-layers having a greater thickness on a portion parallel to the plane of the LED array precursor and a reduced thickness on a portion which is not parallel to the plane of the LED array precursor.