The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Jan. 20, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Yu Lin, Hsinchu, TW;

Chun-Fu Cheng, Hsinchu, TW;

Hsiang-Hung Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 23/528 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 23/5283 (2013.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01);
Abstract

An integrated circuit includes a plurality of transistors and a vertical local interconnection. The transistors include a plurality of gate components, a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side of the integrated circuit than the back-side source/drain epitaxies. The vertical local interconnection connects a first connected-one of the front-side source/drain epitaxies with a second connected-one of the back-side source/drain epitaxies. A covered-one of the gate components is located between the first connected-one and the second connected-one, the covered-one comprises an front-side portion, a back-side portion and a covered portion connecting the front-side portion with the back-side portion, and the vertical local interconnection crosses the covered portion and exposes the front-side portion and the back-side portion.


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