3d semiconductor device, structure and methods with memory arrays and connectivity structures

Abstract

A 3D semiconductor device including: a first level including a first single crystal layer and a memory control circuit including first transistors and control circuit connectivity provided by first, second, and third metal layers; a second level including second transistors (one which includes a metal gate) disposed atop the first level; third transistors disposed atop second transistors with a fourth metal layer disposed atop; a memory array including word-lines, the memory array includes at least four memory mini arrays, where each mini array includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second or third transistors; a connection path from the fourth metal to the third or second metal layer, which includes a via disposed through the second level, and where the memory control circuit includes at least one power down control circuit.