The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

May. 09, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yang Lu, Boise, ID (US);

Yuan He, Boise, ID (US);

Kang-Yong Kim, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4078 (2006.01); G11C 11/406 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4078 (2013.01); G11C 11/40615 (2013.01); G11C 11/4076 (2013.01);
Abstract

Apparatuses and techniques for implementing aspects of a time-varying threshold for usage-based disturbance mitigation. In an example aspect, usage-based disturbance circuitry of a memory device utilizes a threshold that varies over time for detecting conditions associated with usage-based disturbance. By utilizing the time-varying threshold, the usage-based disturbance circuitry can reduce a probability of a waterfall event causing a denial-of-service (DOS) situation. In particular, the time-varying threshold can spread out the refreshing of rows over a longer time period. This enables the memory device to have sufficient resources to service other memory requests while also mitigating usage-based disturbance. In example implementations, the threshold is at least partially randomized, which can make it challenging for a malicious actor to identify and overcome the usage-based disturbance mitigation techniques. Also, techniques for generating the time-varying threshold can be implemented without appreciably increasing a size or cost of the memory device.


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