The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2026
Filed:
May. 22, 2024
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Sundararajan Sankaranarayanan, Fremont, CA (US);
Eric N. Lee, San Jose, CA (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/084 (2016.01); G06F 3/06 (2006.01); G06F 12/0882 (2016.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 3/0611 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 12/0882 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/222 (2013.01); G11C 16/0483 (2013.01);
Abstract
A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.