The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2026
Filed:
Aug. 30, 2022
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Vikas Rana, Pehowa, IN;
Kalyan Chakravarthy Kavalipurapu, Telangana, IN;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 11/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0238 (2013.01); G06F 11/1044 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G06F 2212/202 (2013.01);
Abstract
A memory device includes a first array of Non-Volatile Memory (NVM) cells, a second array of logic NVM cells, and a controller. The second array of logic NVM cells stores instructions for accessing the first array of NVM cells. The controller is configured to execute the instructions stored in the second array of logic NVM cells to perform access operations in the first array of NVM cells.
Quick Actions:
Rana, Vikas. (2026). Memory devices including logic non-volatile memory (U.S. Patent No. 12619527). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12619527
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile