The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Nov. 09, 2023
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Denis Martin, Palo Alto, CA (US);

Bala Tarun Nelapatla, San Jose, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/263 (2006.01); G06F 11/27 (2006.01);
U.S. Cl.
CPC ...
G06F 11/263 (2013.01); G06F 11/27 (2013.01);
Abstract

At least one processor may obtain a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be applied via a shared testing input bus. The at least one processor may next generate a test data sequence including an interleaving of respective task procedures of the plurality of test pattern data sets, where the generating of the test data sequence includes generating sleep instructions for respective cores of the plurality of cores in accordance with the interleaving. The at least one processor may then apply the test data sequence via the shared testing input bus.


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Martin, Denis. (2026). Integrated circuit test pattern interleaving (U.S. Patent No. 12619509). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12619509

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