The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Feb. 18, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Su-Jen Sung, Zhubei City, TW;

Guan-Yao Tu, Hsinchu, TW;

Tze-Liang Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/4857 (2013.01); H01L 23/367 (2013.01);
Abstract

A method includes forming a first bond layer on a first wafer, and forming a first thermal conductive channel extending into the first bond layer. The first thermal conductive channel has a first thermal conductivity value higher than a second thermal conductivity value of the first bond layer. The method further includes forming a second bond layer on a second wafer, and forming a second thermal conductive channel extending into the second bond layer. The second thermal conductive channel has a third thermal conductivity value higher than a fourth thermal conductivity value of the second bond layer. The first wafer is bonded to the second wafer, and the first thermal conductive channel at least physically contacts the second thermal conductive channel. An interconnect structure is formed over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.


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