The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Sep. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Xavier F. Brun, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01);
Abstract

Embodiments described herein include electronic packages. In an embodiment, an electronic package comprises a die and a through substrate via that passes through the die. In an embodiment, the through substrate via is coupled to a backside pad on the die. In an embodiment, a first layer is over the backside pad, where the first layer comprises a first dielectric material. In an embodiment, a second layer is over the first layer, where the second layer comprises a second dielectric material. In an embodiment, a via is through the first layer and the second layer.


Find Patent Forward Citations

Brun, Xavier. (2026). Dielectric bondable chiplet for package architecture including reset via simplification (U.S. Patent No. 12616013). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12616013

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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