The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

May. 02, 2022
Applicants:

Dmitri Evgenievich Nikonov, Beaverton, OR (US);

Chia-ching Lin, Portland, OR (US);

Uygar E. Avci, Portland, OR (US);

Tanay A. Gosavi, Portland, OR (US);

Raseong Kim, Portland, OR (US);

Ian Alexander Young, Olympia, WA (US);

Hai LI, Portland, OR (US);

Ashish Verma Penumatcha, Beaverton, OR (US);

Ramamoorthy Ramesh, Moraga, CA (US);

Darrell G. Schlom, Ithaca, NY (US);

Inventors:

Dmitri Evgenievich Nikonov, Beaverton, OR (US);

Chia-Ching Lin, Portland, OR (US);

Uygar E. Avci, Portland, OR (US);

Tanay A. Gosavi, Portland, OR (US);

Raseong Kim, Portland, OR (US);

Ian Alexander Young, Olympia, WA (US);

Hai Li, Portland, OR (US);

Ashish Verma Penumatcha, Beaverton, OR (US);

Ramamoorthy Ramesh, Moraga, CA (US);

Darrell G. Schlom, Ithaca, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H10B 51/30 (2023.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 62/40 (2025.01); H10D 62/80 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10D 30/701 (2025.01); H10B 51/30 (2023.02); H10D 30/0415 (2025.01); H10D 30/60 (2025.01); H10D 62/40 (2025.01); H10D 62/80 (2025.01); H10D 62/874 (2025.01); H10D 64/033 (2025.01); H10D 64/689 (2025.01);
Abstract

Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.


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