The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Sep. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mekha George, Hillsboro, OR (US);

Seda Cekli, Portland, OR (US);

Kilhyun Bang, Portland, OR (US);

Krishna Ganesan, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/311 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/83 (2025.01); H10P 50/28 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/83 (2025.01); H10P 50/283 (2026.01);
Abstract

Materials and techniques for recessing heterogenous materials in integrated circuit (IC) dies. In an example, a method includes receiving a plurality of adjoining structures over a substrate. The structures comprise first and second outer sidewalls comprising a first material. An inner material and an intervening material is between the first and second outer sidewalls. The inner material is recessed with a first etch to a recess depth. A surface of the first or second outer sidewall is revealed to the recess depth by etching the intervening material with a second etch.


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