One-time-programmable memory device

Abstract

A one-time-programmable (OTP) memory device includes a memory array including an N-type memory cell and a P-type memory cell. The N-type memory cell includes first channel layers and second channel layers. The P-type memory cell includes third channel layers and fourth channel layers. The N-type memory cell and the P-type memory cell further include a first word-line gate structure extending in the Y-direction and wrapping around the first channel layers and the third channel layers, and an anti-fuse gate structure extending in the Y-direction and wrapping around the second channel layers and the fourth channel layers. The OTP memory device further includes a wall structure extending in an X-direction and between the N-type memory cell and the P-type memory cell in the Y-direction. The first channel layers, the second channel layers, the third channel layers, and the fourth channel layers attach on the wall structure.