The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Dec. 16, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kishore Kumar Muchherla, San Jose, CA (US);

Junwyn A. Lacsao, Folsom, CA (US);

Jeffrey S. Mcneil, Nampa, ID (US);

Violante Moschiano, Avezzano, IT;

Paing Z. Htet, Union City, CA (US);

Sead Zildzic, Folsom, CA (US);

Eric N. Lee, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 11/4099 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 11/4099 (2013.01);
Abstract

Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.


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