The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Feb. 06, 2023
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Zi Wang, Dallas, TX (US);

Kwangsoo Han, Austin, TX (US);

Jordan Moxon, Mountain View, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01); G06F 119/06 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01); G06F 2119/06 (2020.01);
Abstract

Aspects of the present disclosure address systems and methods for performing critical region resynthesis with purpose-directed candidate filtering. Data representing an integrated circuit design is accessed along with a threshold constraint defining a power consumption threshold. A first cell is selected from the integrated circuit design. A swapping candidate to evaluate for swapping with the first cell is selected. The swapping candidate comprises at least a second cell. The swapping candidate is evaluated based on a power consumption associated with the swapping candidate and the power consumption threshold. The first cell is swapped with the swapping candidate in the integrated circuit design based on a result of the evaluating. The data representing the integrated circuit design is updated based on the swapping of the first cell with the swapping candidate.


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