The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Dec. 22, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sufiyan Syed, Chennai, IN;

Roger Gramunt, Portland, OR (US);

Jayesh Gaur, Bangalore, IN;

Priyank Deshpande, Redwood City, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/28 (2006.01); G06F 1/3234 (2019.01); G06F 1/329 (2019.01); G06F 9/22 (2006.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/28 (2013.01); G06F 9/223 (2013.01); G06F 9/4806 (2013.01); G06F 9/5027 (2013.01); G06F 1/3243 (2013.01); G06F 1/329 (2013.01); G06F 9/3836 (2013.01); G06F 9/3853 (2013.01); G06F 2209/5014 (2013.01);
Abstract

In one embodiment, an apparatus includes: a plurality of execution circuits to execute and instruct micro-operations (μops), where a subset of the plurality of execution circuits are capable of execution of a fused μop; a fusion circuit coupled to at least the subset of the plurality of execution circuits, wherein the fusion circuit is to fuse at least some pairs of producer-consumer μops into fused μops; and a fusion throttle circuit coupled to the fusion circuit, wherein the fusion throttle circuit is to prevent a first μop from being fused with another μop based at least in part on historical information associated with the first μop. Other embodiments are described and claimed.


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