The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Nov. 08, 2022
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Mauro Giacomini, Bergamo, IT;

Fabio Enrico Carlo Disegni, Spino d'adda, IT;

Rajesh Narwal, Greater Noida, IN;

Pravesh Kumar Saini, Greater Noida, IN;

Mayankkumar Hareshbhai Niranjani, Lathi, IN;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/315 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G01R 31/315 (2013.01); H01L 22/12 (2013.01);
Abstract

An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.


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