The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Sep. 18, 2023
Applicant:

Phoenix Pioneer Technology Co., Ltd., Hsinchu County, TW;

Inventors:

Chu-Chin Hu, Hsinchu County, TW;

Shih-Ping Hsu, Hsinchu County, TW;

Chih-Kuai Yang, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/685 (2026.01); H10W 70/65 (2026.01); H10W 70/66 (2026.01); H10W 72/30 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/685 (2026.01); H10W 70/65 (2026.01); H10W 70/66 (2026.01); H10W 74/111 (2026.01); H10W 90/00 (2026.01); H10W 72/322 (2026.01); H10W 72/352 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 90/794 (2026.01);
Abstract

A component-embedded packaging structure is provided, in which a plurality of metal layers are formed on an inactive surface of a semiconductor chip so as to serve as a buffer portion, and the semiconductor chip is disposed on a carrying portion with the buffer portion via an adhesive. Then, the semiconductor chip is encapsulated by an insulating layer, and a build-up circuit structure is formed on the insulating layer and electrically connected to the semiconductor chip. Therefore, the buffer portion can prevent delamination from occurring between the semiconductor chip and the adhesive on the carrying portion if the semiconductor chip has a CTE (Coefficient of Thermal Expansion) less than a CTE of the adhesive.


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