The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Aug. 31, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Manoj Sastry, Portland, OR (US);

Christopher Gutierrez, Hillsboro, IN (US);

Marcio Rogerio Juliato, Portland, OR (US);

Shabbir Ahmed, Portland, OR (US);

Vuk Lesi, Cornelius, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/40 (2022.01); G06F 1/04 (2006.01); G06F 1/14 (2006.01);
U.S. Cl.
CPC ...
H04L 63/1416 (2013.01); G06F 1/04 (2013.01); G06F 1/14 (2013.01);
Abstract

Techniques for an attack-aware digital twin in a time sensitive network are described. A method includes receiving time information for a network by an attack-aware digital twin (AADT), the AADT to simulate operations of a clock manager for a node in the network based on models of the clock manager, generating model clock control information to adjust a clock to a network time for the network, the model clock control information to contain a malicious time sample introduced by a time desynchronization attack in the network, and removing the malicious time sample from the model clock control information to adjust the clock to the network time for the network. Other embodiments are described and claimed.


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