The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Aug. 11, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rajkishore Barik, Santa Clara, CA (US);

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Xiaoming Chen, Shanghai, CN;

Dhawal Srivastava, Phoenix, AZ (US);

Anbang Yao, Beijing, CN;

Kevin Nealis, San Jose, CA (US);

Eriko Nurvitadhi, Portland, OR (US);

Sara S. Baghsorkhi, San Jose, CA (US);

Balaji Vembu, Folsom, CA (US);

Tatiana Shpeisman, Menlo Park, CA (US);

Ping T. Tang, Edison, NJ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2023.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 16/17 (2019.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/084 (2023.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/3017 (2013.01); G06F 9/3851 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/3895 (2013.01); G06F 16/17 (2019.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/084 (2013.01); G06T 1/20 (2013.01);
Abstract

One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.


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