System and method for optimizing integrated circuit layout based on neural network

Abstract

Disclosed are a system and a method for optimizing integrated circuit layout based on neural network. The system according to an exemplary embodiment of the present disclosure includes: a placement information generation unit generating placement information indicating placement positions of circuit blocks; a placement information filtering unit predicting a minimum substrate area required for placing the circuit blocks according to the generated placement information and when a predicted minimum substrate area does not correspond to a predetermined reference area range, discarding the generated placement information and requesting the placement information generation unit to generate subsequent placement information; and an EDA tool control unit providing the generated placement information to the EDA tool when the predicted minimum substrate area corresponds to the reference area range, and controlling the EDA tool to measure consumption power, performance, and an area of the target integrated circuit based on the generated placement position information.