The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Adwait Purandare, Hillsboro, OR (US);

Ian Steiner, Portland, OR (US);

Vasudevan Srinivasan, Portland, OR (US);

Ankush Varma, Portland, OR (US);

Nikhil Gupta, Portland, OR (US);

Stanley Chen, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 3/0664 (2013.01); G06F 1/324 (2013.01);
Abstract

In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.


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