The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2026
Filed:
Dec. 13, 2023
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Samuel Coward, London, GB;
Theo Drane, El Dorado Hills, CA (US);
George A. Constantinides, Santa Clara, CA (US);
Emiliano Morini, El Dorado Hills, CA (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01);
Abstract
Described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. Automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. A framework is provided to detect non-mux based opportunities and construct more complex clock gating signals.