The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

Nov. 15, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Bo In Noh, Suwon-si, KR;

Jeong Hoon Ahn, Suwon-si, KR;

Yun Ki Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/30 (2026.01); H10W 74/00 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 74/40 (2026.01); H10W 76/63 (2026.01); H10W 90/00 (2026.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H10W 74/121 (2026.01); H10W 70/685 (2026.01); H10W 74/124 (2026.01); H10W 90/00 (2026.01); H10W 72/07252 (2026.01); H10W 72/07352 (2026.01); H10W 72/07353 (2026.01); H10W 72/221 (2026.01); H10W 72/321 (2026.01); H10W 72/332 (2026.01); H10W 72/334 (2026.01); H10W 74/00 (2026.01); H10W 74/10 (2026.01); H10W 74/127 (2026.01); H10W 74/15 (2026.01); H10W 74/40 (2026.01); H10W 76/63 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.


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