The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2026
Filed:
Sep. 22, 2022
International Business Machines Corporation, Armonk, NY (US);
Ruilong Xie, Niskayuna, NY (US);
Kisik Choi, Watervliet, NY (US);
Muthumanickam Sankarapandian, Niskayuna, NY (US);
Shogo Mochizuki, Mechanicville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Self-aligned direct backside contacts by an epitaxy everywhere under source/drain region approach are provided. In one aspect, a semiconductor device includes: a field-effect transistor(s) on a backside interlayer dielectric; an epitaxial contact placeholder in the backside interlayer dielectric that directly contacts a first source/drain region of the field-effect transistor(s); and a self-aligned direct backside contact in the backside interlayer dielectric that directly contacts a second source/drain region of the field-effect transistor(s). The epitaxial contact placeholder extends a distance dinto the backside interlayer dielectric from the first source/drain region, and the self-aligned direct backside contact extends a distance dinto the backside interlayer dielectric from the second source/drain region, where d>d. The field-effect transistor(s) can include a stack of active layers surrounded by a gate, and the first/second source/drain regions on opposite sides thereof. A method of fabricating the present semiconductor device is also provided.