Nor memory cell with floating gate

Abstract

An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a bit line region, a surface region apart from the bit line region in a lateral direction, and a trench region apart from the surface region in the lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate; an electrically conductive control gate; an electrically conductive word line; and a floating gate insulated from the substrate and the word line and comprising: a first tip substantially aligned with the sidewall portion of the trench region of the substrate; and a second tip self-aligned with an edge of the word line that is farthest from the second portion of the control gate.