Static random access memory supporting a dynamically variable duration self-time delay for a single clock cycle read-modify-write operation

Abstract

A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location in response to assertion of control signal having a dynamically variable delay dependent on the current data word. The operations are advantageously performed within a single clock cycle.