The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2026
Filed:
Aug. 25, 2023
Nxp Usa, Inc., Austin, TX (US);
Gary L. Miller, Austin, TX (US);
Devendra Bahadur Singh, Lucknow, IN;
Jonathan Gamoneda, Austin, TX (US);
Paul Kimelman, Alamo, CA (US);
Oded Yishay, Austin, TX (US);
NXP USA, INC., Austin, TX (US);
Abstract
Systems and methods for debugging multi-core processors with configurable isolated partitions have been described. In an illustrative, non-limiting embodiment, an integrated circuit, may include: a plurality of Cross-Trigger Matrices (CTMs) configured to establish a debug network among a plurality of multi-cluster tiles (MCTs), where each MCT includes a plurality of processor cores, and where each processor core is assigned to a respective isolated partition of processor cores; and a System Interface (SI) coupled to the plurality of CTMs, where the SI is configured to control the plurality of CTMs to enable or disable at least a portion of the debug network to allow an isolated partition to be debugged independently of another isolated partition. A method may include enabling or disabling, by the SI, buses between the MCTs to create isolated debug networks, each isolated debug network corresponding to a distinct isolated partition of processor cores.