The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2026
Filed:
Nov. 07, 2024
Micron Technology, Inc., Boise, ID (US);
Rishabh Dubey, Agrate Brianza, IT;
Micron Technology, Inc., Boise, ID (US);
Abstract
A system includes a first memory device; a second memory device; and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including: determining a size of the first memory device designated for storing a plurality of address mapping data structures, wherein each address mapping data structure of the plurality of address mapping data structures is associated with a corresponding namespace of a plurality of namespaces, wherein each namespace of the plurality of namespaces is associated with a corresponding region of a second memory device; associating a first address mapping granularity level with the first memory device for storing a first address mapping data structure of the plurality of address mapping data structures; determining a remaining available space of the first memory device by excluding a first size of the first address mapping data structure from the size of the first memory device, wherein the first size is calculated based on the first address mapping granularity level; and associating, in view of the remaining available space of the first memory device and a remaining available space of the second memory device, a second address mapping granularity level with the first memory device for storing a second address mapping data structure of the plurality of address mapping data structures.
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