The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Feb. 10, 2022
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Douglas Charles La Tulipe, Heverlee, BE;

Anne Jourdain, Grez-Doiceau, BE;

Gaspard Hiblot, Leuven, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 23/544 (2013.01); H01L 2223/54426 (2013.01);
Abstract

The disclosed technology relates to methods for producing an interconnect structure on the back side of an integrated circuit chip. According to a first aspect, a via opening is etched in a top semiconductor layer, and filled with a sacrificial material, thereby forming a sacrificial pillar. Then front and back end of line portions are processed and the substrate is thinned. The etch stop layer and the sacrificial pillar are removed, and replaced an electrically conductive material forming a through semiconductor via. According to a second aspect, the sacrificial pillar is etched through the opening of a trench that intersects the pillar. Filling the trench with a conductive material also fills the cavity created by etching back the pillar resulting in an integral conductive pad and interconnect rail structure. The pillar can be removed and replaced by a conductive material, thereby creating the TSV connection.


Find Patent Forward Citations

La Tulipe, Douglas. (2026). Method for producing a through semiconductor via connection (U.S. Patent No. 12598966). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12598966

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…