Write leveling in ddr memory device and operating method thereof

Abstract

A write leveling system includes a frequency divider, a signal processing circuit, and a data control circuit. The frequency divider is arranged to perform a frequency dividing operation upon a clock signal to generate multiple frequency-divided clock signals. The signal processing circuit is arranged to perform signal processing upon a data strobe signal to generate multiple processed data strobe signals. The data control circuit is arranged to generate a data signal according to the multiple frequency-divided clock signals and the multiple processed data strobe signals, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.