The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Feb. 16, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kuan-Ting Pan, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu, TW;

Shi Ning Ju, Hsinchu, TW;

Chih-Hao Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6757 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/021 (2025.01); H10D 62/118 (2025.01); H10D 64/021 (2025.01); H10D 64/691 (2025.01);
Abstract

A device includes: a first stack of nanostructures; a second stack of nanostructures horizontally offset from the first stack; a first source/drain region abutting the first stack of nanostructures; a second source/drain region abutting the second stack of nanostructures; a wall structure between the first and second stacks and spaced apart from the nanostructures of the first stack; and a first gate structure, which includes: a gate dielectric layer that wraps around the nanostructures of the first stack; and a conductive core layer on the gate dielectric layer, wherein thickness of the conductive core layer between one of the nanostructure of the first stack and the wall structure is in a range of 0 nanometers to 1 nanometer, inclusive.


Find Patent Forward Citations

Pan, Kuan-Ting. (2026). Field effect transistor with isolation structure and method (U.S. Patent No. 12593475). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12593475

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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