The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2026
Filed:
Jun. 13, 2023
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Kiheun Lee, Suwon-si, KR;
Yongseok Kim, Suwon-si, KR;
Hyuncheol Kim, Suwon-si, KR;
Daewon Ha, Suwon-si, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); H10B 51/10 (2023.01); H10D 30/69 (2025.01); H10D 62/84 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); H10B 51/10 (2023.02); H10D 30/701 (2025.01); H10D 62/84 (2025.01); H10D 64/689 (2025.01);
Abstract
A ferroelectric memory device includes a channel layer, a gate insulation layer on the channel layer, and a gate electrode layer on the gate insulation layer. The gate insulation layer includes a ferroelectric inductive layer and a ferroelectric stack structure on the ferroelectric inductive layer, and the ferroelectric stack structure is stacked in an order or reverse order of a ferroelectric layer and a non-ferroelectric layer.