The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Jul. 03, 2024
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jihoon Jeong, Cary, NC (US);

Vinay Patel, Stouffville, CA;

Jae Gon Lee, Mountain View, CA (US);

Akshay Dua, San Jose, CA (US);

Ayush Singh, San Jose, CA (US);

Xiang Hu, San Jose, CA (US);

Sai Akshit Kumar Gampa, Austin, TX (US);

Vishal Srinivasan Iyer, San Jose, CA (US);

Nitin Makhija, San Jose, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0016 (2013.01); H03K 19/018557 (2013.01); H03K 19/0013 (2013.01);
Abstract

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.


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