The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Jan. 09, 2024
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Feng-Min Lee, Hsinchu City, TW;

Yu-Yu Lin, New Taipei City, TW;

PO-Hao Tseng, Taichung City, TW;

Yu-Hsuan Lin, Taichung City, TW;

Wei-Lun Weng, Tainan City, TW;

Wei-Fu Wang, Keelung City, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4096 (2006.01); G11C 5/06 (2006.01); G11C 11/4097 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 5/063 (2013.01); G11C 11/4097 (2013.01);
Abstract

A memory structure includes a plurality of first transistors and a plurality of second transistors. The first transistors are arranged in a first array. First ends of the first transistors are respectively coupled to a plurality of first bit lines, and gates of the first transistors are respectively coupled a plurality of first word lines. The second transistors are arranged in a second array. Gates of the second transistors are respectively coupled to second ends of the first transistors, and second ends and first ends of the second transistors are respectively coupled to second bit lines and second word lines. The first transistors and the second transistors are disposed on a substrate. The first word lines or the first bit lines are extended along a normal direction of a plane of the substrate, and the second word lines or the second bit lines are extended along the normal direction.


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