Non-retention mode leakage reduction without impacting the cell content in the retention mode

Abstract

Techniques for non-retention mode leakage reduction without impacting cell content in a retention mode. A plurality of power gate circuits provide power to respective regions of memory cells. The power gate circuits may be placed physically proximate to the respective regions of the memory cells, and the control circuitry may be placed in a central location of the circuit. The power gate circuits include respective first and second series-connected transistors. Threshold voltages of the first transistors may be less than threshold voltages of the respective second transistors. The first transistors may be controlled independent of the respective second transistors. A third transistor may diode-connect the first transistors, or a subset thereof, in a retention mode. The power gate circuits may include multiple individually controllable first transistors in parallel with one another.