Bank-shared usage-based disturbance circuitry

Abstract

Apparatuses and methods for implementing bank-shared usage-based disturbance circuitry are described. Bank-shared usage-based disturbance circuitry is coupled to the at least two banks of a memory device and can mitigate usage-based disturbance within these banks. To detect a condition associated with usage-based disturbance, the bank-shared usage-based disturbance circuitry selectively reads data associated with usage-based disturbance from one of the at least two banks. To mitigate usage-based disturbance, the bank- shared usage-based disturbance circuitry can selectively cause one or more rows within either of the at least two banks to be refreshed. By using the same circuitry to mitigate usage-based disturbance across multiple banks, the total footprint, complexity, and power consumption of the memory device can be reduced relative to other memory devices that utilize circuitry that is dedicated for each bank. The memory device can therefore be integrated within space-constrained and power-constrained devices such as, for example, portable devices.