The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Aug. 24, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventor:

Amit Kumar, Bangalore, IN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/505 (2013.01); G06F 9/4881 (2013.01); G06F 9/5016 (2013.01);
Abstract

Disclosed herein are method, system, and computer-readable storage-medium embodiments of adaptive scheduling with dynamic partition-load balancing for fast partition compilation. An embodiment includes detecting, by at least one processor, an available hardware-resource amount available to be used by an electronic design automation (EDA) process via a plurality of computing elements, with respect to a design specification, and analyzing the design specification, to generate an estimate of a hardware-resource amount to be used by the EDA process. In some further embodiments the at least one processor may compare the estimate with the available hardware-resource amount, and adjust at least one of a memory allocation for the EDA process or a specified number of computing elements of the plurality of computing elements, for parallel use by the EDA process. Moreover, the at least one processor may calculate a weighted load average for the plurality of computing elements, according to some additional embodiments.


Find Patent Forward Citations

Kumar, Amit. (2026). Adaptive scheduling with dynamic partition-load balancing for fast partition compilation (U.S. Patent No. 12591461). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12591461

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…