The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2026
Filed:
Oct. 18, 2022
Kabushiki Kaisha Toshiba, Tokyo, JP;
Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;
Toru Sugiyama, Tokyo, JP;
Akira Yoshioka, Yokohama Kanagawa, JP;
Hung Hung, Kawasaki Kanagawa, JP;
Yasuhiro Isobe, Tokyo, JP;
Hitoshi Kobayashi, Yamato Kanagawa, JP;
Tetsuya Ohno, Yokohama Kanagawa, JP;
Naonori Hosokawa, Yokohama Kanagawa, JP;
Masaaki Onomura, Setagaya Tokyo, JP;
Masaaki Iwai, Yokohama Kanagawa, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Toshiba Electronic Devices & Storage Corporation, Kawasaki, JP;
Abstract
A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor including a first electrode, a second electrode, and a first control electrode, a normally-on transistor including a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first diode including a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a Zener diode including a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode; a first terminal provided on the semiconductor package, the first terminal being electrically connected to the first electrode; a plurality of second terminals provided on the semiconductor package, the second terminals being electrically connected to the first electrode, and the second terminals being lined up in a first direction; a third terminal provided on the semiconductor package, the third terminal being electrically connected to the fourth electrode; a plurality of fourth terminals provided on the semiconductor package, the fourth terminals being electrically connected to the first control electrode; and a plurality of fifth terminals provided on the semiconductor package, the fifth terminals being electrically connected to the second control electrode, and the fifth terminals being lined up in the first direction.