The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Sep. 09, 2024
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Hitoshi Imi, Yokohama Kanagawa, JP;

Yutaka Horie, Mitaka Tokyo, JP;

Shugo Suzuki, Hanno Saitama, JP;

Yasutomo Sakurai, Kawasaki Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 23/495 (2006.01); H03K 17/16 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H02M 1/08 (2006.01); H10D 1/68 (2025.01); H10D 30/47 (2025.01); H10D 30/60 (2025.01); H10D 62/85 (2025.01);
U.S. Cl.
CPC ...
H01L 25/162 (2013.01); H01L 23/49575 (2013.01); H03K 17/162 (2013.01); H01L 23/3107 (2013.01); H01L 24/48 (2013.01); H01L 2224/48245 (2013.01); H02M 1/08 (2013.01); H10D 1/68 (2025.01); H10D 30/47 (2025.01); H10D 30/60 (2025.01); H10D 62/8503 (2025.01);
Abstract

According to one embodiment, a semiconductor device includes: first, second, and third lead frames; a first transistor which is GaN transistor provided on the first lead frame and electrically connected to the first lead frame; a second transistor which is GaN transistor provided on the second lead frame and electrically connected to the third lead frame; a third transistor which is MOS transistor provided on the third lead frame and electrically connected to the third lead frame and the first transistor; a fourth transistor which is MOS transistor provided on the second lead frame and electrically connected to the second lead frame and the second transistor; and a capacitor electrically connected to the first and the second lead frame; wherein the first, the third, the second, and the fourth transistor are arranged side by side in this order in a first direction.


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