The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Aug. 26, 2022
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Gabriel H. Loh, Bellevue, WA (US);

Raja Swaminathan, Austin, TX (US);

Rahul Agarwal, Livermore, CA (US);

Assignee:

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/16 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/16 (2013.01); H01L 23/528 (2013.01);
Abstract

A semiconductor package assembly includes a die having a front surface and a back surface opposite to and parallel to the front surface. A first portion of a front surface of an interconnect die is coupled to a portion of the back surface of the die. The interconnect die includes a connectivity region that is coupled to one or more through-die vias in the die through the back surface of the die. A spacer component is coupled to a second portion of the front surface of the interconnect die. The spacer component includes conductive connections, with one or more of the conductive connections are coupled to the conductive pathways of the connectivity region of the interconnect die.


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