The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

May. 16, 2023
Applicant:

Omnivision Technologies, Inc., Santa Clara, CA (US);

Inventors:

Chun-Yung AI, San Jose, CA (US);

Kazufumi Watanabe, Mountain View, CA (US);

Chih-Wei Hsiung, San Jose, CA (US);

Assignee:

OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H10F 39/18 (2025.01);
U.S. Cl.
CPC ...
H10F 39/802 (2025.01); H10F 39/807 (2025.01); H10F 39/18 (2025.01); H10F 39/8037 (2025.01);
Abstract

A pixel array substrate includes a semiconductor substrate including a pixel array, a first side, and a second side opposite the first side, a guard ring region in the semiconductor substrate, formed of a doped semiconductor, enclosing the pixel array, and extending into the semiconductor substrate from the first side, and a peripheral region in the semiconductor substrate and enclosing the guard ring region. The peripheral region includes at least one device and a deep trench isolation (DTI) structure region disposed between the guard ring region and the at least one device and proximate to the second side of the semiconductor substrate. The DTI structure region is configured to block an electric current path between a P-N junction in the guard ring region and the at least one device.


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