The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

May. 16, 2023
Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Pascal Chevalier, Chapareillan, FR;

Sebastien Fregonese, Leognan, FR;

Thomas Zimmer, Talence, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/17 (2025.01); H10D 10/01 (2025.01); H10D 10/40 (2025.01); H10D 62/13 (2025.01);
U.S. Cl.
CPC ...
H10D 62/184 (2025.01); H10D 10/01 (2025.01); H10D 10/051 (2025.01); H10D 10/061 (2025.01); H10D 10/421 (2025.01); H10D 62/134 (2025.01); H10D 62/137 (2025.01);
Abstract

A lateral bipolar transistor includes an emitter region doped with a first conductivity type, having a first width and a first average doping concentration; a collector region doped with the first conductivity type, having a second width greater than the first width of the emitter region and a second average doping concentration lower than the first average doping concentration; and a base region positioned between the emitter and collector regions. The emitter, collector and base regions are arranged in a silicon layer on an insulator layer on a substrate. A substrate region that is deprived of the silicon and insulator layers is positioned on a side of the collector region. A bias circuit is coupled, and configured to deliver, to the substrate region a bias voltage. This bias voltage is controlled to modulate an electrostatic doping of the collector region.


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