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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12588220 B1

PDFFull Text
Date of Patent:
Mar. 24, 2026

Filed:

May. 16, 2022

1tir memory with a 3d structure

Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Sylvain Barraud, Grenoble Cedex, FR;

François Andrieu, Grenoble Cedex, FR;

Assignee:

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris, FR;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Britt Hanley

Assistant Examiner:

Jason James Greaving

Int. Cl.
CPC ...
H10B 63/00 (2023.01); G11C 5/06 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10B 61/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/845 (2023.02); G11C 5/063 (2013.01); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10B 61/22 (2023.02); H10B 63/30 (2023.02); H10D 30/0323 (2025.01); H10D 30/6731 (2025.01); H10D 30/6735 (2025.01); H10D 30/6744 (2025.01); H10D 30/6745 (2025.01); H10D 30/6755 (2025.01); H10D 62/118 (2025.01); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 70/021 (2023.02); H10N 70/231 (2023.02); H10N 70/253 (2023.02);
Abstract

A memory is structured in lines and columns over several superimposed levels. Each level includes an array of memory elements and gate-all-around access transistors, each transistor including a semiconductor nanowire and each gate being insulated from the gates of the other levels. The memory also includes conductive portions, each crossing at least two levels and coupled to first ends of the nanowires of one column of the levels; memory stacks, each crossing the levels and coupled to second ends of the nanowires of the column; first conductive lines, each connected to the conductive portions of the same column; and word lines each extending in the same level while coupling together the gates of the same line and located in said level.

Find Patent Forward Citations

Barraud, Sylvain. (2026). 1tir memory with a 3d structure (U.S. Patent No. 12588220). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12588220

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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